Random access memories are usually used as the main computer memory to store instructions and data for fast access by the processing units. In those random access devices, the storage elements are organized in a matrix, sometimes also quoted memory cell array, that facilitates short access times which are independent on the location of the data. A memory cell array is made up of a plurality of bit lines and a plurality of crossing word lines. At the crossing points memory cells are located for the actual storage of the binary states 0 and 1 reflected by logic low and high voltage potentials.
RAM devices are classified into volatile and nonvolatile RAM. The volatile RAM comprises static RAM (SRAM) and employs FLIP-FLOP-based latches as storage elements or memory cells, while the so-called dynamic RAM (DRAM) uses a tiny capacitor with two different charge state levels to represent binary information.
FIG. 1 shows an exemplary DRAM memory chip according to prior art. The memory chip M comprises a memory cell array MCA, a row address decoder RAD, a column address decoder CAD, a control CT, an active-current generator AG and a standby-current generator ST. The memory cell array MCA comprises a plurality of bit lines BL and a plurality of word lines WL of which only one of each is shown as an example. At the crossing points of the word and bit lines, a memory cell MC is situated which comprises an access transistor T and a storage capacitor CS. The access or select transistor T is implemented as a switch controlled by a signal on the word line and connects the storage capacitor CS between the respective bit line BL and a reference potential GND which is chosen as ground, here.
The row address decoder RAD is connected to the word lines for selecting the word lines and has for each word line a respective word line driver WLD. The column address decoder CAD is connected to the bit lines and has a sense amplifier and pre-charge circuit SA for each bit line for reading and writing data from and into the memory cells.
The active-current generator AG or the standby-current generator SG serves as a power supply for the sense amplifiers and pre-charge circuits SA. The control CT is connected by a plurality of lines to a control input IC and an address input IA and a data in- and output BD of the DRAM memory chip M for receiving respective control, address and data signals C, A, D. The control CT sends row address signals RA to the row address decoder RAD and column address signals CA and data signals D to the column address decoder CAD. Further, the control CT is adapted to control the active-current generator AG by a respective power control signal PC.
The active-current generator AG is capable of providing relatively high power to the sense amplifiers and pre-charge circuits SA when a read or write operation is initiated. After a predetermined time period, the active-current generator AG sends a timing signal TS to the standby-current generator SG for taking over the power supply to the sense amplifiers and pre-charge circuits SA. The standby-current generator SG provides a relatively low, but sufficient power to the sense amplifiers and pre-charge circuits SA when no read or write process is active in the memory chip M.
A simplified timing scheme of the switching between the active-current and the standby-current generators AG, SG and the voltage characteristics during an exemplary read process from a memory cell MC on a bit line BL. The upper curve shows the time evolution of the voltage VBL, VBLB on a bit line BL with respect to ground, and the lower curve shows the respective time evolution of a voltage at a complementary bit line BLB. The voltages are normalized with respect to the nominal voltage VBLH corresponding to a logic high. In modern memory chips VBLH is for instance 1.8 volts.
At the time t0, a read command, address and control signals are applied to the memory chip inputs IC, IA, BD and brings the chip into an active state. This means, the active-current generator AG is switched on through a respective power control signal PC by the control CT. Usually, a short-delay time t1 passes until the respective word line driver WLD selects a word line and the select transistor T provides connectivity between the storage capacitor CS and the selected bit line BL. During a time interval t2-t1, the charge stored in the storage capacitor CS is distributed between the inherent capacitance of the bit line and the storage capacitor.
Between the times t2 and t3, a respective sense amplifier amplifies the changing voltage generated by the additional charge on the bit line and brings it to the nominal value VBLH. The analog process occurs for a complementary bit line, wherein in case of a written 1 or logic high in the corresponding complementary memory cell, the voltage on the complementary bit line drops through the redistribution of stored charge in the corresponding storage capacitor and is amplified to 0-level. The voltages on the bit line BL and complementary bit line BLB then represent a logic high.
In memory chips M according to the prior art, the active-current generator AG switches itself off after an elapsed time t4 after activation and contemporaneously switches the standby-current generator SG on for providing power to the sense amplifiers and pre-charge circuits. The time t4 is usually in the order of a hundred nanoseconds after activation. The power supply of the sense amplifiers and pre-charge circuits can be switched to the low power standby-current generator, because power is in particular consumed during the amplification phase between t1 and t3. When the active power generators are switched off after t4—mainly due to leakage between neighboring bit lines or other acceptable defects—the voltage at the bit line decreases until a pre-charge operation is executed. During a pre-charge, the respective word line is deselected, i. e. the select transistor de-couples the storage capacitor from the bit line such that the current voltage at t5 or the corresponding charge in the storage capacitor CS is stored in the memory cell. Contemporaneously, the voltage at the bit line is pre-charged to exactly one half of the nominal bit line high voltage VBLH. This time t5 is set to about 80 microseconds complying to industry standards for DRAM memories.
Before delivering memory chips to customers, tests of their proper functioning have to be performed. It is in particular important to test the serviceability of all the bit lines and their respective sense amplifiers and pre-charge circuits. This is usually done by writing a state into the memory cell and waiting a significant time after the active-current generator is switched off. Then, at a time t5 a pre-charge is executed and then the written data into the respective memory cell is read out and compared to the test data. If the bit line sense amplifier and pre-charge circuit works properly, both data, the test data and read-out data are the same. However, should there occur any significant and undesired leakage between bit lines or sense amplifiers are defective, the written test data and read-out data differ from each other.
However, this method of testing the serviceability of the bit line infrastructure in a memory chip according to the prior art has a major disadvantage: for every bit line to be tested, a minimum amount of time of t4 has to be invested until the decrease of the voltage on a bit line can be detected in a test by repeated read-outs of the test data. Since such lengthy chip testing deteriorates the throughput of a DRAM memory device production, faster test methodes are desired.